The present invention relates to noise-shaping digital amplifiers, and specifically to techniques for gating the resonant output stage of such amplifiers. It should be noted at the outset that although the invention is described herein with reference to a band pass (e.g., RF) implementation, the present invention is also applicable to other amplifier configurations such as, for example, base band audio amplifiers or motor drive circuits.
FIG. 1 shows a band pass noise-shaping amplifier designed according to techniques described in U.S. Pat. No. 5,777,512 for METHOD AND APPARATUS FOR OVERSAMPLED, NOISE-SHAPING, MIXED-SIGNAL PROCESSING issued Jul. 7, 1998, the entire disclosure of which is incorporated herein by reference for all purposes. The top and bottom side FETs 102 and 104 are alternately driven by gating signals which are generated from the output of A/D converter 106 by gate drive circuitry 108. If FETs 102 and 104 are driven by a switching signal, e.g., a square wave, the parasitic gate capacitances of each device result in heavy and undesirable losses which are proportional to the frequency of the gate signal, the gate capacitance, and the square of the input voltage, i.e., fcv2 losses. Thus, inductors 110 are included in series with each FET gate to resonate out the fcv2 losses. A frequency selective network 112 provides noise shaping for the amplifier in conjunction with a continuous-time feedback path 114. According to a specific embodiment, network 112 comprises one or more resonator stages.
While this results in a reduction of these undesirable losses, there are additional undesirable consequences. First, an undesirable and substantial overshoot (or undershoot) voltage is generated at the input of each FET at gate signal transitions. Second, each gate transition starts a resonance at each gate which wants to continue virtually indefinitely. If the amplifier is intended only to generate a regular pattern of alternating 0s and 1s (as with frequency and phase modulation applications), this resonance is not a problem (if one can live with the overshoot/undershoot) in that it results in the desired bit pattern. For applications in which nonperiodic patterns of bits are desired, this resonance interferes with generation of the desired bit pattern.
It is therefore desirable to provide techniques by which such devices may be switched without suffering from the undesirable effects of traditional techniques for mitigating fcv2 losses.
According to the present invention, because the series inductor is desirable for reducing fcv2 losses at FET gates, the present invention provides a technique whereby the gate drive circuitry controls the gate signal to overcome the overshoot and resonance problems. That is, the leading and trailing edges of gate pulses generated by the gate drive circuitry are temporarily brought to the desired logic level, brought back to the original logic level, and then brought back to the desired logic level once the signal level at the FET gate has settled at the desired level. To generalize, the present invention employs control logic and an inductor to charge the logic state of a gate capacitor.
Thus, the present invention provides methods and apparatus for switching a switch from a first logic state to a second logic state. The switch has a gate terminal having a gate capacitance and a resistance associated therewith. According to various embodiments, this resistance can be any combination of the input resistance of the switch and external series or parallel resistors. The gate terminal also has a series inductance coupled thereto. While the switch is in the first logic state, a pulse corresponding to the second logic state is applied to the inductance. The pulse has a first level of energy associated therewith which is sufficiently high to overcome damping by the resistance (thus allowing the gate terminal to reach a signal level corresponding to the second logic state thereby switching the switch to the second logic state), and sufficiently low to mitigate oscillation due to the inductance and the gate capacitance (such that the gate terminal settles at the signal level before a subsequent transition of the switch to the first logic state).
A further understanding of the nature and advantages of the present invention may be realized by reference to the remaining portions of the specification and the drawings.